R. Sakthivel ¹, M. Vanitha ², Sneha Singh ¹

Affiliations
1 School of Electronics Engineering, Vellore - 632014, Tamil Nadu, IN
2 School of Information and Technology, Vellore - 632014, Tamil Nadu, IN

Abstract

The work proposed in this paper is to reduce the leakage power by using Gate Length Biasing (GLB) technique in a Vedic multiplier. The Gate Length Biasing Technique (GLB) is used to reduce the leakage power by increasing the channel length marginally which in turn increases the delay linearly. As the leakage power reduces a small amount of delay increases which can be ignored. Here Gate Length Biasing (GLB) technique is implemented on a standard cell i.e., NOR standard cell. Then the results are compared with GLB and without GLB. The standard cell with GLB is implemented on digital circuit for application purpose. The digital circuit in which the NOR standard cell is implemented is the 8x8 bit Vedic multiplier. The leakage power with Gate Length Biasing is found to be lesser than the leakage power without gate length biasing technique.

Keywords

Gate Length Biasing Technique, Leakage Power, Standard Cell, Vedic Multiplier

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Y. Premson ¹, R. Sakthivel ¹

Affiliations
1 VIT University, Vellore – 632014, Tamil Nadu, IN

Abstract

Background/Objectives: Due to the huge volume of data involved, it is very much challenging to design efficient contrast enhancement algorithms in real time applications. In this paper an efficient hardware is presented for image enhancement. Methods/Statistical analysis: The computation algorithms are based on the calculations of image Probability Density Function (PDF) and Cumulative Distribution Function (CDF). For better results weighted PDF and smoothed CDF computations are performed. Then the adaptive gamma correction is used for enhancing the image contrast. A compensated CDF is used as the adaptive gamma parameter. To reduce hardware complexity, approximation techniques are employed. In the modified algorithm, the bi-histogram equalization is utilized. Xilinx system generator is used for hardware co-simulation. The hardware is implemented on an FPGA based 'Zed Board'. Findings: The hardware oriented method achieves similar quality image as the software approach and the results are qualitatively and quantitatively analyzed. The PDF and CDF based computations are faster than other image processing methods. So this algorithm is suitable for real time applications. The image is found to have a better quality in the modified AGCWD method. The PSNR value also is found to be better than the normal method. But the hardware utilization of the modified algorithms is found to be higher than the normal algorithm. The bi-histogram approach is suitable to preserve the mean brightness of the original image. Applications/Improvements: Future works may modify the proposed method, for reducing the hardware requirements. Contrast enhancement is one of the crucial image processing techniques in high definition image and video applications. Image enhancement techniques find applications in LED and LCD display processing, medical image analysis etc.

Keywords

Adaptive Gamma Correction, Contrast Enhancement, Histogram Modification, Weighting Distribution, Zed Board

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Kishore Sanapala ¹, R. Sakthivel ¹

Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Background/Objectives: As technology scaling down, subthreshold operation is playing a vital role in the design of digital circuits to achieve ultra low power consumption with considerable performance. Methods/Statistical Analysis:This paper presents a novel body bias technique, where the body terminal of NMOS is reverse biased to VDD which reduces the subthreshold leakage. The basic logic gates are designed using proposed body bias scheme. To analyze the performance, standard 28 transistor full adder cell is implemented using the proposed technique and the performance parameters - power, delay, PDP are calculated and compared with the conventional CMOS Full adder. The simulations are done in cadence 90 nm technology for VDD = 0.2v. Findings: The simulation results show that the circuits designed using the proposed technique achieves more than 31% savings in power and more than 15% savings in PDP than traditional body bias technique used in static CMOS configuration. Applications/Improvements: These circuits are widely applicable in portable battery operated devices such as cellular phones, wearable electronics and remote sensors where ultra low power consumption is required with low to medium performance.

Keywords

Body Bias, CMOS, Full Adder, Logic Gates, Subthreshold Operation, Ultra Low Power

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G . Ragunath ¹, R. Sakthivel ¹

Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Background/Objectives: XOR gate is a primary element in binary adders because which is used to detect sum – output. In this paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical analysis: Usually a half adder (HA) circuit is designed with one XOR and one AND gate but if  this modified XOR is used in HA, the design requires only one XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives better result when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA, binary to excess-1 converter (BEC) based sqrt CSLA and optimized logic based (OLB) sqrt CSLA. The results show that Area – Delay – Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BEC based sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements:  These adders can be used in Arithmetic Logic Unit (ALU) of a micro-processor as a binary adder.

Keywords

Application Specific Integrated Circuits (ASIC), Area Efficient, Low Power, Sqrt CSLA, XOR Gate

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